Voltage multiplier circuit for UHF RF to DC conversion for RFID applications

The application domain of passive radio frequency identification (RFID) is continuously growing. Hence, the Energy Harvesting has become an attractive approach to ensure that there is sufficient energy available to run the system. In the passive RFID, this energy is harvested by converting the radio frequency (RF) energy into a DC signal received from surrounding. This conversion is performed using a module known as RF-to-DC rectifier. In this work, we are using a high efficiency differential drive CMOS rectifier which is the well established circuit used in RF-to-DC conversion. In order to generate a high DC voltage the cascading of RF to DC rectifier is performed. This arrangement is known as a voltage multiplier (VM). The purpose of this work is to propose a simple and effective method to form the VM arrangement. The proposed VM arrangement is designed in a standard 0.18/μm CMOS technology and simulations are performed using the Cadence spectre simulator. The proposed VM arrangement is implemented in 2, 4, 6 and 8 stages and compared it with Conventional Voltage Multiplier (CVM) with similar stages. We have used a Voltage Conversion Efficiency/Stage (VCES) at the capacitive load of InF and Power Conversion Efficiency (PCE) for a current load of 5μA as a figure of comparison between these two arrangements. It is evident from the simulation that proposed VM arrangement exhibit ≈ 31% raise in VCES, with approximately double PCE as compared to CVM arrangement.