Analyzing Worst-case Delay-Buffer-Equation for wormhole networks on chip

In wormhole network-on-chip, the mathematical relationship of buffer and worst-case end-to-end delay (called Worst-case Delay-Buffer-Equation, WDBE) is very important for design space exploration. However, traditionally simulation-based and queuing theory based methods can not derive the WDBE directly. In this paper, we propose a network calculus-based method to analyze WDBE. First, we present analytical models of WDBE derivation for primitive scenarios. For complex scenarios, we use the contention tree model to divide them into primitive scenarios, and get the WDBE step by step. As an example, we detail the WDBE analysis procedure. Finally, the experiments show the correctness and potential of our proposed method.