Optimization of modulator and circuits for low power continuous-time Delta-Sigma ADC

This paper presents a new optimization method for achieving a minimum current consumption in a continuous-time Delta-Sigma analog-to-digital converter (ADC). The method is applied to a continuous-time modulator realised with active-RC integrators and with a folded-cascode operational transconductance amplifier (OTA). Based on a detailed circuit analysis of the integrator and the OTA, key expression are derived relating the biasing current of the OTA to the noise requirements of the integrator. In the optimization the corner frequency of the modulator loop filter and the number of quantizer levels are swept. Based on the results of the circuit analysis, for each modulator combination the summed current consumption of the 1st integrator and quantizer of the ADC is determined. By also sweeping the partitioning of the noise power for the different circuit parts, the optimum modulator and circuit solution that fulfils a predefined set of performance requirements at minimum current is found. A design example is provided for a 3rd order modulator, achieving for the OTA of the 1st integrator and the quantizer a summed current consumption of 28 μA. An SNR of 84.3 dB in the 20 kHz audio band was achieved, when considering the noise from the 1st integrator and the quantizer.