Implementation of a dynamic wordlength SIMD multiplier

This paper presents an efficient design method to construct a flexible, high band-width, and multi-wordlength multiplier. The method includes a new sticky Booth coding technique to tackle the unscalability problem in traditional Booth coding for multi-wordlength multiplier design. Moreover, a cell array based architecture is developed for efficient implementation of the multiplier, which can be conveniently combined with standard power management techniques to achieve both high speed, high flexibility and low power. As a case study, a multiplier supporting 3 operation modes (one 64 ×64, four 32×32, and sixteen 16×16) has been designed based on the introduced methodology. The synthesis results with 40nm CMOS shows 5% in speed improvement and 7.1 % in area efficiency improvement, comparing to state-of-the-art industrial multi-wordlength multipliers. The applicability and suitability of the proposed multiplier has been analyzed in a soft-defined radio platform where the power efficiency can be easily improved under dynamic transmission scenarios.