High-voltage pulse-triggered SR latch level-shifter design considerations

This paper compares pulse-triggered level shifters with a traditional level-triggered topology for high-voltage applications with supply voltages in the 50 V to 100 V range. It is found that the pulse-triggered SR (Set/Reset) latch level-shifter has a superior power consumption of 1800 μW/MHz translating a signal from 0-3.3 V to 87.5-100 V. The operation of this level-shifter is verified with measurements on a fabricated chip. The shortcomings of the implemented level-shifter in terms of power dissipation, transition delay, area, and startup behavior are then considered and an improved circuit is suggested which has been designed in three variants being able to translate the low-voltage 0-3.3 V signal to 45-50 V, 85-90 V, and 95-100 V respectively. The improved 95-100 V level shifter achieves a considerably lower power consumption of 438 μW/MHz along with a significantly lower transition delay. The 45-50 V version achieves 47.5 μW/MHz and a transition delay of only 2.03 ns resulting in an impressive FOM of 2.03ns/(0.35 μm 50 V) = 0.12ns/μmV.