Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools

Asynchronous circuit design is well understood but design tools supporting asynchronous design are largely lacking, and designers are limited to using conventional EDA-tools. These tools have a built-in synchronous mind-set and this complicates their use for asynchronous implementation. One example is the key role that clock signals play in specifying time-constraints for the synthesis. In this paper explain how we handled the synthesis and layout of an asynchronous network-on-chip for a multi-core platform. Focus is on the design process while the actual NOC-design and its performance are presented elsewhere.