Stimuli generator for testing processes in VHDL

Verification is the most crucial part of the chip design process. Test benches, which are used to test VHDL code, need perform efficiently and effectively. Each process in VHDL is executed in parallel. This concept introduces problems of how to test and verify complex systems. We present the new framework TestBenchMulti that is able to generate test stimuli for parallel VHDL designs. The experiments were carried out on synthesizable VHDL circuits at the behavioral level. The obtained code coverage results were confirmed in the real implementation using Xilinx FPGA hardware.