• DocumentCode
    1792496
  • Title

    Highly sensitive, low-power, 10-20Gb/s transimpedance amplifier based on cascaded CMOS inverter gain stages

  • Author

    Rakowski, M. ; Ingels, M. ; De Meyer, K. ; Steyaert, M. ; Absil, P. ; Van Campenhout, J.

  • Author_Institution
    IMEC, Leuven, Belgium
  • fYear
    2014
  • fDate
    4-7 May 2014
  • Firstpage
    115
  • Lastpage
    116
  • Abstract
    Error-free operation is demonstrated up to 20Gb/s for a TIA consisting of seven cascaded inverter-based gain stages in 40nm (LP) CMOS technology, with a current sensitivity of 70μA and an energy efficiency of 575fJ/b.
  • Keywords
    CMOS analogue integrated circuits; invertors; low-power electronics; operational amplifiers; cascaded CMOS inverter gain stages; current sensitivity; energy efficiency; error-free operation; low-power transimpedance amplifier; size 40 nm; Bandwidth; CMOS integrated circuits; Gain; Inverters; Optical sensors; Sensitivity; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Optical Interconnects Conference, 2014 IEEE
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    978-1-4799-2467-7
  • Type

    conf

  • DOI
    10.1109/OIC.2014.6886106
  • Filename
    6886106
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1792496