Modeling, simulation and hardware implementation of fault current limiter in single phase and three phase lines for compensating voltage sag

A high potential fault current levels in power grid is not a new approach, and should eventually exceed, the limitation of short-circuit-current would be existed protection devices. Different to pricey system upgrades of protection devices, Fault Current Limiters (FCL´s) gives an additional cost-efficient solutions to forestall recent protection devices and different instrumentality on the system from being broken by excessive fault currents. Evaluation of short circuit faults may usually the origin of voltage sags at a purpose of common coupling point (PCC) during a power network, the extent of the voltage sag is proportional to the short current level, reducing the fault current level at intervals the networks will scale back voltage sags throughout faults and defend sensitive loads that are interfaced to a similar PCC. The planned structure prevents voltage sag and counter balance the phase-angle of the PCC once fault prevalence. As a result, different feeders which are interlinked to the sub-station PCC can have attentive power quality. During this paper a high performance 3-phase fault current electrical model is planned. A Matlab/Simulink model is developed and simulation results are conferred. Finally a computer simulated results are conclusive through prototype design.