Low frequency noise in surface and buried channel nanometric CMOS transistors

In this study the electrical and noise characteristics of surface and buried channel N-type MOSFETs are widely investigated and compared. Various operation modes which can exist at the surface of a buried channel devices, such as accumulation, depletion, and inversion, are demonstrated. We show that buried channel devices require careful selection of the biasing point to achieve optimal noise performance. Avoiding either inversion or accumulation at the interface is required to minimize the noise. The input-referred current noise power spectral density of the investigated buried channel transistor is shown to be a factor of 20 lower at low frequencies than in surface channel device.