DocumentCode
1793529
Title
High throughput transmitter architecture for DVB-S2
Author
Malka, Haim ; Hochma, Shahar ; Lifshitz, Nir
Author_Institution
Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
fYear
2014
fDate
3-5 Dec. 2014
Firstpage
1
Lastpage
4
Abstract
In this paper we present a full implementation of DVB-S2 transmitter. The architecture that we are suggesting can support 24 bits per clock cycle, which translates to about 3.4Gbps using a 140MHz clock. The transmitter was implemented on Virtex-6 ML605 evaluation board.
Keywords
digital video broadcasting; hardware description languages; phase shift keying; transmitters; 8-PSK modulation; DVB-S2 transmitter; VHDL; Virtex-6 ML605 evaluation board; digital video broadcasting; forward error correcting code; frequency 140 MHz; high throughput transmitter architecture; Clocks; Digital video broadcasting; Finite impulse response filters; Modulation; Parity check codes; Throughput; Transmitters; DVB-S2 Transmitter VHDL Implementation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical & Electronics Engineers in Israel (IEEEI), 2014 IEEE 28th Convention of
Conference_Location
Eilat
Print_ISBN
978-1-4799-5987-7
Type
conf
DOI
10.1109/EEEI.2014.7005891
Filename
7005891
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