Area optimization of cryptographic algorithm on less dense reconfigurable platform

Author

Mulani, Altaf O. ; Mane, P.B.

Author_Institution

Dept. of Electron. & Telecommun., Sinhgad Coll. of Eng., Pune, India

fYear

2014

fDate

9-9 Oct. 2014

Firstpage

86

Lastpage

89

Abstract

Reconfigurable computing has grown to become a large and important field of research. Implementing network security algorithms on reconfigurable platform provides major benefits over VLSI and software platforms since they offers high speed similar to VLSI and high flexibility similar to software platforms. The paper presents efficient implementation of DES algorithm on XC25200 FPGA. The synthesis result shows that with this kind of implementation only 2118 slices and 97 number of bonded IOBs are utilized as compared to 2151 slices and 186 number of bonded IOBs with normal implementation.

Keywords

VLSI; cryptography; field programmable gate arrays; optimisation; reconfigurable architectures; DES algorithm; VLSI; XC2S200 FPGA; area optimization; bonded IOB; cryptographic algorithm; less dense reconfigurable platform; network security algorithms; reconfigurable computing; software platforms; Algorithm design and analysis; Encryption; Field programmable gate arrays; Hardware; IP networks; Software; Software algorithms; FPGA; Reconfigurable hardware; VLSI; cryptographic algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Smart Structures and Systems (ICSSS), 2014 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4799-6506-9

Type

conf

DOI

10.1109/ICSSS.2014.7006201

Filename

7006201