Title :
A 16 × 16 Cellular Logical Network with partial reconfiguration feature
Author :
Yeniceri, Ramazan ; Abtioglu, Emrah ; Govem, B. ; Yalcin, Mustak E.
Author_Institution :
Dept. of Electron. & Commun. Eng., Istanbul Tech. Univ., Istanbul, Turkey
Abstract :
Partial Reconfiguration (PR) has been providing a new lever in digital designs since that feature emerged with practical tools. Similar to changing the program running on a microprocessor, partial reconfiguration is changing the hardware configured on a Field Programmable Gate Array in run-time. In this paper, a Cellular Logical Network performing Boolean functions in order to execute trigger-wave evolution is proposed. The network is endowed with PR feature, thus the functions of the cells are changed by reconfiguring them. That relieves us of the complex cell design in which all possible functions are embedded.
Keywords :
Boolean functions; field programmable gate arrays; logic design; Boolean functions; PR feature; cell design; cellular logical network; digital design; field programmable gate array; microprocessor; partial reconfiguration feature; trigger-wave evolution; Arrays; Boundary conditions; Clocks; Field programmable gate arrays; Microprocessors;
Conference_Titel :
Cellular Nanoscale Networks and their Applications (CNNA), 2014 14th International Workshop on
Conference_Location :
Notre Dame, IN
DOI :
10.1109/CNNA.2014.6888620
