Comparison of low-complexity image compression algorithms for analog circuit implementation

CMOS imaging hardware has become a widespread research topic due to its flexibility in allowing focal-plane, pixel-level signal processing. In a number of vision chips, dedicated image processing techniques are carried out in the analog domain to extract relevant information. Analog processing leads to time and power consumption savings, especially if combined with parallel processing, which is conventionally used because of the inherently parallel nature of imaging arrays. We focus on the focal-plane analog implementation of an image compression algorithm, based on differential pulse-code modulation, linear transform, and vector quantization. In a prototype fabricated in a 0.35 μm CMOS technology, the texture information inside each pixel block in a 32 × 32 array was locally encoded by inner products applied to 4 × 4 pixel neighborhoods followed by vector quantization. In this paper, a new chip implemented in a 0.18 μm CMOS technology incorporating improvements suggested by the previous prototype experimental evaluation is presented. We highlight a 5 dB increase in image quality, confirmed by numerical simulations, at the expense of modest increase in complexity and bit rate. Cascode current mirrors are used in parts of the circuitry and pixel non-linearity models are made available to the decoder.