Memristor-CMOS reconfigurable multiplier architecture

Hardware multipliers are an essential component of signal processes and related algorithms embedded within numerous multimedia and communication systems. This paper presents memristor-CMOS based reconfigurable multiplier architecture having a variable bit-width computational capability. The approach provides the much needed flexibility in configuration of the multiplier array with the added advantage of reduced chip area by some 18%. The performances of the proposed architecture is presented using memristor SPICE model and 180 nm CMOS process using 1.8 V supply voltage.