Analysis of Permanent Faults in Transaction Level SystemC Models

Since SoC systems are typically used for critical scenarios, it is desirable to analyze the impact of faults on them. However, fault-impact analysis is difficult due to the high integrity of SoC systems and different levels of abstraction provided by modern system design languages such as SystemC. In this paper, we present a method for modeling and analyzing permanent faults in SystemC TLM programs. The proposed method includes three steps, namely timed model extraction, fault modeling, and fault analysis. We use UPPAAL timed automata to formally model the SystemC TLM programs and monitor how the models behave in the presence of faults. A case study is also provided to better explain our proposed approach.