Sustainability assurance modeling for SRAM-based FPGA evolutionary self-repair

A quantitative stochastic design technique is developed for evolvable hardware systems with self-repairing, replaceable, or amorphous spare components. The model develops a metric of sustainability which is defined in terms of residual functionality achieved from pools of amorphous spares of dynamically configurable logic elements, after repeated failure and recovery cycles. At design-time the quantity of additional resources needed to meet mission availability and lifetime requirements given the fault-susceptibility and recovery capabilities are assured within specified constraints. By applying this model to MCNC benchmark circuits mapped onto Xilinx Virtex-4 Field Programmable Gate Array (FPGA) with reconfigurable logic resources, we depict the effect of fault rates for aging-induced degradation under Time Dependent Dielectric Breakdown (TDDB) and interconnect failure under Electromigration (EM). The model considers a population-based genetic algorithm to refurbish hardware resources which realize repair policy parameters and decaying reparability as a complete case-study using published component failure rates.