Extending bufferless on-chip networks to high-throughput workloads

Bufferless networks-on-chip (NoC) has been proposed to reduce network cost by removing router input buffers and improve energy-efficiency. However, bufferless NoC has some limitations that include lower network throughput caused by deflection routing at high load. In addition, the longer router critical path impacts the router frequency, which reduces the amount of bandwidth provided by the network router. These limitations reduce any benefit of bufferless NoC - especially for high-throughput workloads such as GPGPU. In this work, we first provide a simple analysis into how the benefit of bufferless NoC can be reduced for high throughput workloads, especially in terms of energy-efficiency. We then propose clumsy flow control (CFC) - a congestion control mechanism that can reduce the amount of deflection and improve the efficiency of bufferless NoC. The clumsy flow control enables the allocation to be simplified and we propose a novel switch allocation (randomized-deterministic allocation) which significantly reduces the router critical path. The combination of these two techniques result in our bufferless NoC to exceed the system performance of buffered network by approximately 7% (up to 22%) while reducing network area by 53% and energy by 52%.