DocumentCode
1796834
Title
An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs
Author
Gaoming Du ; Miao Li ; Zhonghai Lu ; Minglun Gao ; Chunhua Wang
Author_Institution
Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China
fYear
2014
fDate
17-19 Sept. 2014
Firstpage
49
Lastpage
56
Abstract
Reorder buffers are often needed in multi-path routing networks-on-chips (NoCs) to guarantee in-order packet delivery. However, the buffer sizes are usually over-dimensioned, due to lack of worst-case analysis, leading to unnecessary larger area overhead. Based on network calculus, we propose an analysis framework for the worst-case reorder buffer size in multi-path minimal routing NoCs. Experiments with synthetic traffic and an industry case show that our method can effectively explore the traffic splitting space, as well as the mapping effects in terms of reorder buffer size with a maximum improvement of 36.50%.
Keywords
buffer circuits; network routing; network-on-chip; NoCs; in-order packet delivery; multipath minimal routing; network calculus; networks-on-chips; reorder buffer size; synthetic traffic; traffic splitting space; worst-case analysis; Analytical models; Calculus; Delays; Mathematical model; Out of order; Routing; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Networks-on-Chip (NoCS), 2014 Eighth IEEE/ACM International Symposium on
Conference_Location
Ferrara
Type
conf
DOI
10.1109/NOCS.2014.7008761
Filename
7008761
Link To Document