A 0.43pJ/bit true random number generator

Author

Ting-Kuei Kuan ; Yu-Hsuan Chiang ; Shen-Iuan Liu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2014

fDate

10-12 Nov. 2014

Firstpage

33

Lastpage

36

Abstract

A small-area energy-efficient true random number generator (TRNG) is presented. This TRNG introduces a jitter signal generator to realize the noise pre-amplification, and utilizes a metastable latch to resolve the jitter edges. Moreover, to tolerate the process and environment variations, an offset calibration is employed to dynamically correct the bias of the probability of logic 0/1 in background. A prototype is fabricated in 40-nm CMOS technology. It occupies an area of 0.0014mm² and consumes 214nW from a 0.8-V supply at a throughput of 500kbps. The proposed TRNG passes the NIST tests, and its calculated FOM is 0.43pJ/bit.

Keywords

CMOS logic circuits; calibration; jitter; random number generation; signal generators; CMOS technology; NIST tests; TRNG; bit rate 500 kbit/s; environment variations; jitter signal generator; logic probability; noise pre-amplification; offset calibration; power 214 nW; size 40 nm; small-area energy-efficient true random number generator; voltage 0.8 V; Calibration; Generators; Jitter; Latches; NIST; Noise; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian

Conference_Location

KaoHsiung

Print_ISBN

978-1-4799-4090-5

Type

conf

DOI

10.1109/ASSCC.2014.7008853

Filename

7008853