AES implementation for RFID Tags: The hardware and software approaches

Author

Hongsongkiat, Thanapol ; Chongstitvatana, Prabhas

Author_Institution

New Product Res. Dept., Silicon Craft Technol. Co., Ltd., Bangkok, Thailand

fYear

2014

fDate

July 30 2014-Aug. 1 2014

Firstpage

118

Lastpage

123

Abstract

This work presents two different implementations of 128-bit AES cryptography for RFID tags: hardware module and software program. The hardware AES module has been designed with 0.13 um CMOS technology at 1.5 V. The size of the module is 7229 equivalent gates, and the maximum throughput is 130 Mbps. The power consumption at 125 kHz is 6 uA, which meets specification for low-power RFID tags at low frequency. The software version is implemented on a custom 8-bit microcontroller. The program is written in assembly language with our proprietary instruction set. It can process AES encryption in 6,012 instructions, which takes 20,601 clock cycles, using 2 kBytes of instruction memory and 320 Bytes of data memory. It is targeted to use in high-frequency RFID applications.

Keywords

CMOS integrated circuits; cryptography; microcontrollers; power consumption; radiofrequency identification; AES cryptography; AES encryption; AES implementation; CMOS technology; RFID tags; bit rate 130 Mbit/s; clock cycles; custom 8-bit microcontroller; data memory; frequency 125 mHz; hardware AES module; hardware module; high-frequency RFID; instruction memory; power consumption; size 0.13 mum; software program; voltage 1.5 V; Clocks; Encryption; Generators; Hardware; Logic gates; Polynomials; Software; AES; ASIC; RFID; low-power;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Engineering Conference (ICSEC), 2014 International

Conference_Location

Khon Kaen

Print_ISBN

978-1-4799-4965-6

Type

conf

DOI

10.1109/ICSEC.2014.6978180

Filename

6978180