A 23mW/lane 1.2–6.8Gb/s multi-standard transceiver in 28nm CMOS

Author

Seong-Ho Lee ; Tran, Duke ; Ali, Tamer ; Catli, Burak ; Heng Zhang ; Wei Zhang ; Abdul-Latif, Mohammed ; Zhi Huang ; Guansheng Li ; Ahmadi, Mahmoud Reza ; Momtaz, Afshin

Author_Institution

Broadcom® Corp., China

fYear

2014

fDate

10-12 Nov. 2014

Firstpage

105

Lastpage

108

Abstract

This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2-6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI. Power consumption per lane is 23mW at 0.9V for SATA3 at 6Gb/s, with an area of 0.265mm² for a single-lane transceiver with PLL.

Keywords

CMOS integrated circuits; low-power electronics; phase locked loops; radio transceivers; CMOS technology; PCIE; PLL; QSGMII; RXAUI; SATA; SGMII; USB3; XAUI; bit rate 1.2 Gbit/s to 6.8 Gbit/s; circuit technique; communication standards; low-power multistandard transceiver design; power 23 mW; power consumption; single-lane transceiver; voltage 0.9 V; CMOS integrated circuits; Clocks; Jitter; Phase locked loops; Receivers; Standards; Transceivers; clock and data recovery; high speed integrated circuits; serializer-deserializers; transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian

Conference_Location

KaoHsiung

Print_ISBN

978-1-4799-4090-5

Type

conf

DOI

10.1109/ASSCC.2014.7008871

Filename

7008871