Title :
Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology
Author :
Guan-Sing Chen ; Chin-Yang Wu ; Chen-Lun Lin ; Hao-Wei Hung ; Jri Lee
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Fully-integrated 40-Gb/s pulse pattern generator (PPG) and bit-error-rate tester (BERT) chipsets has been presented in 65-nm CMOS technology. Using external clock inputs, the PPG and BERT achieve full operation with ultra-wide data range from 40 Mb/s to 40 Gb/s. Built-in PLL and CDR circuits are also included to provide robustness for standard specification testing.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; error statistics; phase locked loops; pulse generators; test equipment; CDR circuits; CMOS technology; PLL circuits; bit error rate tester chipsets; bit rate 40 Mbit/s to 40 Gbit/s; external clock; fully integrated pulse pattern generator; size 65 nm; ultrawide data range; Bit error rate; Boosting; CMOS integrated circuits; Clocks; Gain; Jitter; Temperature sensors;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008872
