DocumentCode :
1796986
Title :
A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory
Author :
Athmanathan, Aravinthan ; Stanisavljevic, Milos ; Cheon, Jaeseung ; Kang, Sook-Yang ; Ahn, Choon Ki ; Yoon, Jinsu ; Shin, M. ; Kim, T. ; Papandreou, Nikolaos ; Pozidis, Haris ; Eleftheriou, Evangelos
Author_Institution :
IBM Res. - Zurich, Riischlikon, Switzerland
fYear :
2014
fDate :
10-12 Nov. 2014
Firstpage :
137
Lastpage :
140
Abstract :
Multiple-Level Cell (MLC) storage provides increased capacity and hence reduced cost-per-bit in memory technologies, thereby rendering such technologies suitable for big data applications. In Phase-Change Memory (PCM), however, MLC storage is seriously hampered by the phenomenon of resistance drift. We present a readout circuit for PCM specifically designed for drift resilience in MLC operation. Drift resilience is achieved through the use of specific non-resistance-based cell-state metrics which, in contrast to the traditional cell-state metric, i.e., the low-field electrical resistance, have built-in drift robustness. The circuit provides a fast and efficient implementation of drift-resilient metric, enabling, for the first time, the performance required by non volatile memory applications. In addition, by exploiting the non linear sub-threshold I-V characteristics of PCM cells, the readout architecture promises to increase the distinguishable signal range. The proposed read circuitry is designed and fabricated in 64-nm CMOS technology. Experimental results using an integrated test resistor array for readout circuit characterization are presented, demonstrating access time of 450 ns at 6-bit raw (5-bit effective) resolution. The circuit has low-noise characteristics and does not exhibit sensitivity to bit-line parasitics. The readout circuit is co-integrated with a 16 Mb 2x-nm PCM cell array and the necessary programming electronics.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit manufacture; logic design; phase change memories; readout electronics; CMOS; drift resilience; drift-resilient readout scheme; multiple-level cell storage; non volatile memory; phase-change memory; readout circuit; size 64 nm; time 450 ns; word length 6 bit; Computer architecture; Measurement; Microprocessors; Phase change materials; Phase change memory; Resistance; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
Type :
conf
DOI :
10.1109/ASSCC.2014.7008879
Filename :
7008879
Link To Document :
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