A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS

Author

Ching-Wei Wu ; Ming-Hung Chang ; Chia-Cheng Chen ; Lee, Razak ; Hung-Jen Liao ; Chang, Joana

Author_Institution

Memory Develop Project (MDP), Taiwan Semicond. Manuf. Co. (TSMC), Hsinchu, Taiwan

fYear

2014

fDate

10-12 Nov. 2014

Firstpage

145

Lastpage

148

Abstract

This paper presents a configurable SRAM for low voltage operation supporting both pseudo two-port SRAM (P2P-SRAM) and single-port SRAM (SP-SRAM) functions in one compiler. Unlike conventional pseudo two-port SRAM that always performs read first, this work enables dynamic read-or-write-first selection and write-through function. It can improve SP-SRAM function speed by 90% faster than that of the conventional read-first pseudo two-port SRAM design. An area-free constant-negative-level write driver (CNL-WD), which is suitable for compiler development, is used to improve write Vmin for configuration range from 4 to 256 cells/BL. A testchip is fabricated in a 16nm Fin-FET CMOS technology with a 0.0907μm² 6T-SRAM cell.

Keywords

CMOS memory circuits; MOSFET circuits; SRAM chips; driver circuits; 6T-SRAM cell; CNL-WD; FinFET CMOS technology; P2P-SRAM function; SP-SRAM function; area-free constant-negative-level write driver; configurable 2-in-1 SRAM compiler; dynamic read-or-write-first selection; low voltage operation; pseudotwo-port SRAM function; read-first pseudotwo-port SRAM design; single-port SRAM function; size 16 nm; write-through function; Arrays; CMOS integrated circuits; Capacitors; Clocks; SRAM cells; Voltage measurement; compiler; configurable; low Vmin; negative-level; pseudo two-port SRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian

Conference_Location

KaoHsiung

Print_ISBN

978-1-4799-4090-5

Type

conf

DOI

10.1109/ASSCC.2014.7008881

Filename

7008881