A 1–100Mb/s 0.5–9.9mW LDPC convolutional code decoder for body area network

Author

Chih-Lung Chen ; Sheng-Jhan Wu ; Hsie-Chia Chang ; Chen-Yi Lee

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2014

fDate

10-12 Nov. 2014

Firstpage

229

Lastpage

232

Abstract

A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1~100Mb/s with power consumption of 0.5~9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.

Keywords

CMOS integrated circuits; Zigbee; body area networks; convolutional codes; forward error correction; low-power electronics; parity check codes; power consumption; CMOS technology; FEC candidate; IEEE 802.15.4g; IEEE 802.15.6; Viterbi decoder; bit rate 1 Mbit/s to 100 Mbit/s; body area network; error correcting performance; forward error correction; low power LDPC convolutional code decoder; power 0.5 mW to 9.9 mW; power consumption; shift-shared memory architecture; silicon area; size 90 nm; supply voltage; voltage 0.6 V; Convolutional codes; Decoding; Forward error correction; IEEE 802.15 Standards; Power demand; Semiconductor device measurement; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian

Conference_Location

KaoHsiung

Print_ISBN

978-1-4799-4090-5

Type

conf

DOI

10.1109/ASSCC.2014.7008902

Filename

7008902