Title :
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop
Author :
Chien-Kai Kao ; Kuan-Lin Fu ; Shen-Iuan Liu
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 2×25 Gb/s clock and data recovery circuit is fabricated in a 40-nm CMOS process. A background amplitude-locked loop is proposed to reduce the amplitude variation of a charge-steering-logic return-to-zero latch. The measured rms jitter is 2.26 ps and the peak-to-peak jitter is 15.56 ps for a 25 Gb/s PRBS of 27-1. It dissipates 8.8 mw per channel from 1.15 V supply.
Keywords :
CMOS logic circuits; clock and data recovery circuits; flip-flops; CMOS process; amplitude variation reduction; background amplitude-locked loop; bit rate 25 Gbit/s; charge-steering-logic return-to-zero latch; clock and data recovery circuit; size 40 nm; time 2.26 ps; voltage 1.15 V; Capacitors; Clocks; Jitter; Latches; Resistance; Semiconductor device measurement; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008915
