A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS

Author

Cheng-En Hsieh ; Shen-Iuan Liu

Author_Institution

Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2014

fDate

10-12 Nov. 2014

Firstpage

325

Lastpage

328

Abstract

A 0.3V 10-bit rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC) is realized in 0.18-μm CMOS process. While the supply is 0.3V, a double-boosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. To lower the power, differential dynamic switches are used to control the splitting capacitors of the digital-to-analog converter. This ADC achieves the SNDR of 54.57dB and the SFDR of 69.89dB, respectively. The power consumes 15.9nW at 5kS/s from a 0.3V supply. A figure-of-merit of 7.3fJ/conversion-step for this ADC is achieved.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); semiconductor switches; CMOS process; analog-to-digital converter; conversion time; conversion-step SAR ADC; differential dynamic switches; digital-to-analog converter; double-boosted sampling switch; figure-of-merit; power 15.9 nW; rail-to-rail successive approximation register; size 0.18 mum; splitting capacitors; supply-boosted time-domain comparator; voltage 0.3 V; word length 10 bit; CMOS integrated circuits; Capacitors; Solid state circuits; Switches; Switching circuits; Time-domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian

Conference_Location

KaoHsiung

Print_ISBN

978-1-4799-4090-5

Type

conf

DOI

10.1109/ASSCC.2014.7008926

Filename

7008926