DocumentCode :
1797089
Title :
A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration
Author :
Xinwang Zhang ; Zhihua Wang ; Baoyong Chi
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear :
2014
fDate :
10-12 Nov. 2014
Firstpage :
353
Lastpage :
356
Abstract :
A 0.1-1.5GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity, and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8 phase local oscillating (LO) generator, the highest carrier frequency from the frequency synthesizer is only twice of the desired LO frequency. The HR receiver has been implemented in 65nm CMOS. With 1.8mm2 core chip area and 5.4-24.5mA current consumption from a 1.2V power supply, the receiver achieves 85dB conversion gain, 4.3dB NF, +13dBm/+14dBm IB/OB-IIP3, >54/56 dB HR3/HR5 with 30-40dB improvement by calibration, and 2.3% EVM with 32QAM modulation signal.
Keywords :
CMOS integrated circuits; UHF integrated circuits; UHF mixers; frequency synthesizers; quadrature amplitude modulation; radio receivers; CMOS; LO generator; QAM modulation signal; current 5.4 mA to 24.5 mA; frequency 0.1 GHz to 1.5 GHz; frequency synthesizer; gain 85 dB; harmonic rejection receiver; local oscillating generator; phase ambiguity correction; phase mismatch; size 1.8 mm; size 65 nm; vector gain calibration; voltage 1.2 V; Calibration; Frequency measurement; Gain; Harmonic analysis; Mixers; Power harmonic filters; Receivers; LO generator; harmonic rejection; opamp; phase ambiguity; receiver;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
Type :
conf
DOI :
10.1109/ASSCC.2014.7008933
Filename :
7008933
Link To Document :
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