A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET

Author

Ikeda, Shoji ; Sang-yeop Lee ; Ito, H. ; Ishihara, Noboru ; Masu, Kazuya

Author_Institution

Tokyo Inst. of Technol., Yokohama, Japan

fYear

2014

fDate

10-12 Nov. 2014

Firstpage

365

Lastpage

368

Abstract

This paper proposes a low voltage sub-sampling PLL with dynamic threshold MOSFET (DTMOS). DTMOS switch can achieve higher on/off ratio, which prevents signal attenuation and leakage of a sub-sampling phase detector (SSPD) under low supply voltage. The proposed SSPD also employs double-balanced structure to suppress feedthrough in hold mode. DTMOS switches are also applied to a sub-sampling charge pump to reduce undesirable current leak. The proposed PLL was fabricated in a 65nm CMOS. Under the power supply of 0.52V, it shows a in-band phase noise of -98 dBc/Hz at 410 kHz, and the total power consumption of 1.72 mW at 5.71 GHz including frequency-locked loop.

Keywords

charge pump circuits; field effect transistor switches; phase detectors; phase locked loops; DTMOS switch; SSPD; dynamic threshold MOSFET; frequency 5.71 GHz; frequency-locked loop; low noise subsampling PLL; low voltage subsampling PLL; power 1.72 mW; signal attenuation; size 65 nm; subsampling charge pump; subsampling phase detector; voltage 0.52 V; Frequency locked loops; Phase locked loops; Phase noise; Power demand; Switches; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian

Conference_Location

KaoHsiung

Print_ISBN

978-1-4799-4090-5

Type

conf

DOI

10.1109/ASSCC.2014.7008936

Filename

7008936