Multilevel semantic foundation for digital logic diagrams

Progress in computer and network capabilities and increased complexity of applications have driven hardware design practice to higher levels of abstraction. In addition, a high-level description of hardware specification is needed for architectural decisions, reuse, understanding, documentation, and communication. Poorly understood schemata can cause a range of problems, from a nonfunctional circuit to electric shock. Currently, many traditional types of representation for logic gates, circuits, and architectural diagrams are standardized and in use; however, these are arbitrary and heterogeneous schematic symbols and conventions that need written explanations, usually in English, of the functions of components and configurations. They reflect a focus on wiring and interconnection but not on functionality. This paper aims at providing a systematic and uniform semantic foundation for logic schemata that can serve at different levels of abstraction. The paper proposes a new diagrammatic description for physical processes, transistors, circuits, and architectural schemata. Initial results demonstrate the viability of the proposed methodology for representation of transistors, gates, and circuits.