A feasibility study of novel packaging technology for low cost and high performance systems

Author

Iguchi, Daisuke ; Umekawa, Hideyuki

Author_Institution

Electr. Device Eng., Fuji Xerox Co., Ltd., Ebina, Japan

fYear

2014

fDate

4-6 Nov. 2014

Firstpage

118

Lastpage

121

Abstract

We have introduced a packaging technology utilizing high-dielectric ultra thin film between power and ground planes not as an embedded capacitor but a low impedance power distribution route directly connected to the chip. In this study the Power Distribution Network (PDN) characteristics of this structure were analyzed in detail using 3-d electromagnetic modeling in order to evaluate the feasibility of this technology. The calculated PDN impedance of the interposer used in the previous study shows good agreement with the measured impedance. Then we introduce a generic modeling technique of PDN for large scale System on Chips (SoCs) and extensive parametric study was done to determine the optimized structure and parameters for power distribution of actual SoCs.

Keywords

electronics packaging; high-k dielectric thin films; integrated circuit interconnections; system-on-chip; 3d electromagnetic modeling; PDN characteristics; PDN impedance; SoC; ground planes; high-dielectric ultra thin film; interposer; large scale system on chips; low impedance power distribution route; packaging technology; power distribution network characteristics; Capacitors; Impedance; Inductance; Packaging; Power distribution; Semiconductor device measurement; System-on-chip; capacitor; power distribution network; power integrity; system on chip;

fLanguage

English

Publisher

ieee

Conference_Titel

CPMT Symposium Japan (ICSJ), 2014 IEEE

Conference_Location

Kyoto

Print_ISBN

978-1-4799-6194-8

Type

conf

DOI

10.1109/ICSJ.2014.7009624

Filename

7009624