Title :
Design and demonstration of large 2.5D glass interposer for high bandwidth applications
Author :
Sakai, Tadashi ; Sawyer, Brett ; Hao Lu ; Takagi, Yutaka ; Furuya, Ryuta ; Suzuki, Yuya ; Kobayashi, Masato ; Smet, Vanessa ; Sundaram, Venky ; Tummala, Rao
Author_Institution :
Fujitsu Labs. Ltd., Atsugi, Japan
Abstract :
In this paper, a large 2.5D glass interposer is demonstrated with 50 um chip-level interconnect (FLI), 3/3 um line and space (L/S) escape routing, and six metal layers, which are targeted for JEDEC high bandwidth memory (HBM). Our routing design suggests that double sided panel processing with 3/3 um L/S can accommodate required signal lines for HBM. Then, 3/3 um L/S transmission lines on 25mm × 30mm glass interposers with 300 um core thickness can be realized by utilizing semi additive process. Finally, 10mm × 10m dies with daisy chains can be successfully bonded to 25mm × 30mm glass interposer with 6 metal lines using copper microbumps with SnAg solder caps.
Keywords :
chip scale packaging; glass; integrated circuit interconnections; network routing; FLI; HBM; JEDEC high bandwidth memory; L-S escape routing; L-S transmission lines; SnAg solder caps; chip-level interconnect; copper microbumps; daisy chains; double sided panel processing; large 2.5D glass interposer; line and space escape routing; metal layers; metal lines; routing design; semi additive process; size 3 mum; size 300 mum; size 50 mum; Assembly; Bandwidth; Fabrication; Glass; Metals; Routing; Silicon; 2.5D assembly; fine routing; glass interposer;
Conference_Titel :
CPMT Symposium Japan (ICSJ), 2014 IEEE
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-6194-8
DOI :
10.1109/ICSJ.2014.7009629
