On automated generation of checker units from hardware assertion languages

This work investigates how assertion-based verification methods applied to simulations can also be used at application runtime. Such approach can be useful to speed-up verification as well as to implement hardware runtime monitors with respect to safety-critical applications. Existing tools and other related work are presented as well as two use cases which have been developed to benchmark the different approaches. The applicability of such flows in real-world applications is discussed, as well as possible traps and pitfalls when generating hardware out of hardware assertion languages. Finally, an outlook to future work based on the current results is given.