Title :
Execution Drafting: Energy Efficiency through Computation Deduplication
Author :
Mckeown, Michael ; Balkind, Jonathan ; Wentzlaff, David
Author_Institution :
Princeton Univ., Princeton, NJ, USA
Abstract :
Computation is increasingly moving to the data enter. Thus, the energy used by CPUs in the data centeris gaining importance. The centralization of computation in the data center has also led to much commonality between the applications running there. For example, there are many instances of similar or identical versions of the Apache web server running in a large data center. Many of these applications, such as bulk image resizing or video Transco ding, favor increasing throughput over single stream performance. In this work, we propose Execution Drafting, an architectural technique for executing identical instructions from different programs or threads on the same multithreaded core, such that they flow down the pipe consecutively, or draft. Drafting reduces switching and removes the need to fetch and decode drafted instructions, thereby saving energy. Drafting can also reduce the energy of the execution and commit stages of a pipeline when drafted instructions have similar operands, such as when loading constants. We demonstrate Execution Drafting saving energy when executing the same application with different data, as well as different programs operating on different data, as is the case for different versions of the same program. We evaluate hardware techniques to identify when to draft and analyze the hardware overheads of Execution Drafting implemented in an Open SPARC T1 core. We show that Execution Drafting can result in substantial performance per energy gains (up to 20%) in a data center without decreasing throughput or dramatically increasing latency.
Keywords :
computer centres; multi-threading; pipeline processing; power aware computing; Apache Web server; CPU; OpenSPARC T1 core; architectural technique; computation centralization; computation deduplication; data center; drafted instruction decoding; drafted instructions; energy efficiency; energy reduction; energy saving; execution drafting; hardware overhead analysis; hardware overhead drafting; hardware technique evaluation; identical instruction execution; latency improvement; loading constants; multithreaded core; pipeline commit stage; pipeline execution stage; switching reduction; throughput reduction; Hardware; Instruction sets; Pipelines; Servers; Switches; Synchronization; Throughput; Cloud Computing; Computation Deduplication; Data Center Computing; Energy Efficiency; Energy Efficient Computing; Microarchitecture; Multithreading;
Conference_Titel :
Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium on
Conference_Location :
Cambridge
DOI :
10.1109/MICRO.2014.43