• DocumentCode
    1799906
  • Title

    Loop-Aware Memory Prefetching Using Code Block Working Sets

  • Author

    Fuchs, Adi ; Mannor, Shie ; Weiser, Uri ; Etsion, Yoav

  • fYear
    2014
  • fDate
    13-17 Dec. 2014
  • Firstpage
    533
  • Lastpage
    544
  • Abstract
    Memory prefetchers predict streams of memory addresses that are likely to be accessed by recurring invocations of a static instruction. They identify an access pattern and prefetch the data that is expected to be accessed by pending invocations of the said instruction. A stream, or a prefetch context, is thus typically composed of a trigger instruction and an access pattern. Recurring code blocks, such as loop iterations may, however, include multiple memory instructions. Accurate data prefetching for recurring code blocks thus requires tight coordination across multiple prefetch contexts. This paper presents the code block working set (CBWS) prefetcher, which captures the working set of complete loop iterations using a single context. The prefetcher is based on the observation that code block working sets are highly interdependent across tight loop iterations. Using automated annotation of tight loops, the prefetcher tracks and predicts the working sets of complete loop iterations. The proposed CBWS prefetcher is evaluated using a set of benchmarks from the SPEC CPU2006, PARSEC, SPLASH and Parboil suites. Our evaluation shows that the CBWS prefetcher improves the performance of existing prefetchers when dealing with tight loops. For example, we show that the integration of the CBWS prefetcher with the state-of-the-art spatial memory streaming (SMS) prefetcher achieves an average speedup of 1.16× (up to 4× ), compared to the standalone SMS prefetcher.
  • Keywords
    iterative methods; performance evaluation; storage management; CBWS prefetcher; PARSEC suites; Parboil suites; SMS prefetcher; SPEC CPU2006 suites; SPLASH suites; access pattern; code block recurring; code block working set prefetcher; code block working sets; data prefetching; loop iterations; loop-aware memory prefetching; memory instructions; memory prefetchers; spatial memory streaming prefetcher; static instruction; tight loop iterations; trigger instruction; Benchmark testing; Hardware; History; Prefetching; Runtime; Tracking loops; Vectors; CBWS; Cache; Differentials; Loops; Prefetching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium on
  • Conference_Location
    Cambridge
  • ISSN
    1072-4451
  • Type

    conf

  • DOI
    10.1109/MICRO.2014.27
  • Filename
    7011415