DocumentCode :
1799914
Title :
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models
Author :
Lustig, Daniel ; Pellauer, Michael ; Martonosi, Margaret
Author_Institution :
Princeton Univ., Princeton, NJ, USA
fYear :
2014
fDate :
13-17 Dec. 2014
Firstpage :
635
Lastpage :
646
Abstract :
We present Pipe Check, a methodology and automated tool for verifying that a particular micro architecture correctly implements the consistency model required by its architectural specification. Pipe Check adapts the notion of a "happens before" graph from architecture-level analysis techniques to the micro architecture space. Each node in the "micro architecturally happens before" (μhb) graph represents not only a memory instruction, but also a particular location (e.g., Pipeline stage) within the micro architecture. Architectural specifications such as "preserved program order" are then treated as propositions to be verified, rather than simply as assumptions. Pipe Check allows an architect to easily and rigorously test whether a micro architecture is stronger than, equal in strength to, or weaker than its architecturally-specified consistency model. We also specify and analyze the behavior of common micro architectural optimizations such as speculative load reordering which technically violate formal architecture-level definitions. We evaluate Pipe Check using a library of established litmus tests on a set of open-source pipelines. Using Pipe Check, we were able to validate the largest pipeline, the Open SPARC T2, in just minutes. We also identified a bug in the O3 pipeline of the gem5 simulator.
Keywords :
formal specification; multiprocessing systems; pipeline processing; program verification; software architecture; μhb graph; O3 pipeline; OpenSPARC T2; PipeCheck; architectural specification; architecturally-specified consistency model; architecture-level analysis techniques; formal architecture-level definitions; gem5 simulator; memory consistency models; memory instruction; memory location; microarchitectural enforcement specification; microarchitectural enforcement verification; microarchitectural optimizations; microarchitecturally-happens-before graph; microarchitecture space; open-source pipelines; pipeline stage; preserved-program order; speculative load reordering; Buffer storage; Load modeling; Mathematical model; Microarchitecture; Pipelines; Program processors; Radio frequency;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium on
Conference_Location :
Cambridge
ISSN :
1072-4451
Type :
conf
DOI :
10.1109/MICRO.2014.38
Filename :
7011423
Link To Document :
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