DocumentCode :
1800255
Title :
Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise
Author :
Lin, Hsiu-Ting ; Wen, Jen-Yang ; Li, James ; Chang, Ming-Tung ; Tsai, Min-Hsiu ; Huang, Sheng-Chih ; Tseng, Chih-Mou
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ.
fYear :
2008
fDate :
28-30 Oct. 2008
Firstpage :
1
Lastpage :
1
Abstract :
Excessive peak power supply noise (PPSN) causes yield loss problem during test. To reduce PPSN, we proposed a new technique called Capture and Shift Toggle Reduction (CASTR). CASTR performs power reduction during dynamic test compaction so the test length overhead is very small. It also includes pseudo Boolean optimization (PBO) and random-based techniques to improve the results. Experimental results show that we can reduce flip-flop toggles, which is highly correlated with PPSN, by 33.4% during shift mode and 41.2% in capture operation simultaneously for the large ISCAS89 benchmarks.
Keywords :
Boolean algebra; automatic test pattern generation; flip-flops; integrated circuit noise; optimisation; CASTR; automatic test pattern generation; capture and shift toggle reduction; dynamic test compaction; flip-flop toggles; peak power supply noise; power reduction; pseudo Boolean optimization; Automatic test pattern generation; Benchmark testing; Compaction; Electronic equipment testing; Logic; Noise reduction; Performance evaluation; Power engineering and energy; Power generation; Power supplies;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1089-3539
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2008.4700701
Filename :
4700701
Link To Document :
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