DocumentCode :
1800362
Title :
A new approach of coding to improve speed and noise tolerance of on-chip busses
Author :
Pillement, Sebastien ; Sentieys, Olivier
Author_Institution :
IRISA/INRIA, Univ. of Rennes, Lannion
fYear :
2008
fDate :
25-27 March 2008
Firstpage :
1
Lastpage :
6
Abstract :
This paper introduces a new coding scheme that faces simultaneously different issues of interconnection design (power, noise and crosstalk). Based on skewing signals on the link, its implementation is very simple and area-efficient. This scheme permits to double bandwidth and to improve noise tolerance through the use of two error detecting codes. The first one uses temporal redundancy and the second one is a parity-based detecting code. This noise tolerance property enables to decrease the power supply voltage to reduce power consumption.
Keywords :
crosstalk; error detection codes; integrated circuit design; integrated circuit interconnections; noise (working environment); parity check codes; crosstalk; error detecting codes; interconnection design; noise tolerance; on-chip busses; parity-based detecting code; power consumption reduction; power supply voltage; skewing signals; CMOS technology; Capacitance; Circuit noise; Crosstalk; Energy consumption; Integrated circuit interconnections; Noise reduction; Power supplies; Voltage; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008. 3rd International Conference on
Conference_Location :
Tozeur
Print_ISBN :
978-1-4244-1576-2
Electronic_ISBN :
978-1-4244-1577-9
Type :
conf
DOI :
10.1109/DTIS.2008.4540226
Filename :
4540226
Link To Document :
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