Title :
A critical look at design guidelines for SOI logic gates
Author :
Kanj, Rouwaida ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
Design guidelines for static and domino SOI CMOS are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-Si. Published design fixes for eliminating parasitic bipolar induced upset are shown to be imperfect. PHI predischarge is thus proposed as an improved method for eliminating data upset due to both bipolar leakage and charge sharing.
Keywords :
CMOS logic circuits; logic design; logic gates; silicon-on-insulator; PHI predischarge; Si; bipolar leakage; charge sharing; design guidelines; domino SOI CMOS; parasitic bipolar induced upset elimination; static SOI CMOS; CMOS logic circuits; CMOS technology; Circuit simulation; Delay effects; Guidelines; Logic design; Logic functions; Logic gates; MOSFETs; Silicon on insulator technology;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010210
