FPGA-accelerated simulation of truncated-matrix multipliers

Truncated-matrix multipliers offer significant reductions in area, power and delay, at the expense of increased computational error. Extensive bit-accurate simulation is often necessary to evaluate the trade-offs and choose the best parameters for a particular application. This paper presents a method for simulating truncated-matrix multipliers using a field-programmable gate array (FPGA). The method is applicable to most error correction methods published to date, and is simple to implement. It enables real-time simulation in actual applications, exhaustive simulation of large design spaces, and Monte Carlo simulation with more trials than other simulation options. When implemented in a Virtex-5 FPGA, the simulation runs at the same speed as a standard round-to-nearest multiplier, performing more than 229 simulations per second per embedded multiplier.