A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels

Lattice decoding algorithms have been proposed for implementing the maximum likelihood detector (MLD), which is the optimal receiver for multiple-input multiple-output (MIMO) channels. However the computational complexity of direct implementation of the lattice decoding algorithm is high and the throughput is variable. In this work, a K-best algorithm is proposed to implement the lattice decoding. It is computational inexpensive and has fixed throughput. It can be easily implemented in a pipelined fashion and has similar performance as the optimal lattice decoding algorithm if high value of K is used. In this paper, we describe a pipelined VLSI architecture for the implementation of the K-best algorithm. The architecture was designed and synthesized using a 0.35 μm library. For a 4-transmit and 4-receive antennas system using 16-QAM, a decoding throughput of 10 Mbit/s can be achieved.