A high-speed FFT processor for OFDM systems

Author

Son, Byung S. ; Jo, Byung G. ; Sunwoo, Myung H. ; Kim, Yong Serk

Author_Institution

Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon, South Korea

Volume

3

fYear

2002

fDate

2002

Abstract

This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed architecture uses a single-memory for a small hardware size and uses a radix-4 algorithm for high speed. Its memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. The architecture has been modeled by VHDL and logic synthesis has been performed using the Samsung^™ 0.5μm SOG cell library (KG80). The implemented FFT processor consists of 98,326 gates excluding RAM. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6μs.

Keywords

OFDM modulation; cellular arrays; digital arithmetic; digital signal processing chips; fast Fourier transforms; hardware description languages; high-speed integrated circuits; logic CAD; memory architecture; 0.5 micron; 256-point complex FFT; 42 MHz; 6 mus; KG80; OFDM systems; SOG cell library; VHDL; butterfly inputs; butterfly outputs; hardware size; high-speed FFT processor; in-place memory strategy; logic synthesis; orthogonal frequency-division multiplexing; radix-4 algorithm; Computer architecture; Digital modulation; Discrete Fourier transforms; Hardware; Memory architecture; OFDM modulation; Pipelines; Random access memory; Telecommunication computing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010215

Filename

1010215