DocumentCode :
1800585
Title :
A design of multi-core system based on Avalon bus
Author :
Zhou, Qian ; Song, Yu-kun ; Zhang, Duo-Ii ; Du, Gao-Ming
Author_Institution :
Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China
Volume :
3
fYear :
2011
fDate :
24-26 Dec. 2011
Firstpage :
1456
Lastpage :
1459
Abstract :
With the development of a large scale integrated circuit and semiconductor production process, multi-processor on-chip system provides a feasible solution for the highly parallel computation and communications. In this paper, taking JPEG decoding as the starting point, a decoding system with multi-core processors based on the Avalon bus is presented. The paper also introduced the principle of JPEG decoding briefly and the hardware architecture of this system. And we also analyze the parallel process of JPEG decoding. Based on it, to verify the resource comparison, it is compared with the JPEG decoding system based on the AHB bus with 4-core on the EP2S180 FPGA development board. According to the experiments, the JPEG decoding system based on the Avalon bus with multi-core takes up less resource, and compared with the system based on the Avalon BUS with single-core, the total decoding time of the same four pictures of this system saves about 66.7%.
Keywords :
decoding; field programmable gate arrays; image coding; multiprocessing systems; system buses; system-on-chip; AHB bus; Avalon bus; EP2S180 FPGA development board; JPEG decoding; decoding system; hardware architecture; multicore system design; multiprocessor on-chip system; Decoding; Multicore processing; Multiplexing; Random access memory; Transform coding; Avalon bus; JPEG decoding; Multi-Core; Nios II; Parallel processing; SoPC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Science and Network Technology (ICCSNT), 2011 International Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4577-1586-0
Type :
conf
DOI :
10.1109/ICCSNT.2011.6182240
Filename :
6182240
Link To Document :
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