Optimizing CMOS operational transconductance amplifiers through heuristic programming

High performance operational transconductance amplifier (OTA) structures for high-speed, low-voltage, sigma- delta modulator applications are designed using two methods. Folded cascode OTA was designed using both g_m/I_D methodology and a novel heuristic. Objective functions and constraints were derived from analytical equations. Results obtained thanks to the proposed heuristic are better than those reached using the g_m/I_D method. Using a 0.35 mum CMOS processing technology, the optimized folded cascode OTA, biased with 2 V power supply, achieved 537 MHz unity-gain frequency, 290 V/s Slew Rate and 85 dB gain, when loaded with a 0.1 pF load capacitances.