An efficient architecture for accumulator-based test generation of SIC pairs

The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns is favorable for sequential fault testing. In this paper a novel implementation for the generation of SIC pairs is presented. The proposed implementation is based on Ling adders that are utilized in current data paths due to their high speed of operation. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.