Title :
Study and implementation of multi-VDD power reduction technique
Author :
Musab, Mohammed ; Yellampalli, Siva
Author_Institution :
VTU Ext. Centre, UTL Technol. Ltd., Bangalore, India
Abstract :
Advances in VLSI technology has led to design of complex circuits, these complex circuits consumes high power. Several traditional methods such as power gating, clock gating, multi VT, variable VT etc., exists to reduce power dissipation. This paper studies Multi-VDD power reduction technique and implements the same for ISCAS89 S38417 benchmark circuit. From the experimental results, Multi VDD technique reduces the power by 85.83% when compared with single VDD.
Keywords :
VLSI; low-power electronics; ISCAS89 S38417 benchmark circuit; VLSI technology; clock gating; complex circuits; multiVDD power reduction technique; power dissipation; power gating; Application specific integrated circuits; Benchmark testing; Clocks; Computers; Delays; Informatics; Power dissipation; ASIC design flow; area; common power format (CPF); dynamic power; level shifters; library; power domains (PD); register transfer logic (RTL); static power; synopsis design constraint file (SDC); timing; tool command language (TCL);
Conference_Titel :
Computer Communication and Informatics (ICCCI), 2015 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-6804-6
DOI :
10.1109/ICCCI.2015.7218149
