Comparative analysis of various off-chip bus encoding techniques

As the number of transistors in the chip has reached 2 billion, the power dissipation becomes the bottleneck in chip design, as power increases, the thermal dissipation also increases which in turn reduces the reliability of the chip and increases the packaging cost. Nowadays various power reduction techniques are adopted to target the power. Bus encoding technique is one among which reduces the dynamic power by reducing the switching activity in off chip wires. Various algorithms for bus encoding are proposed, this paper compares the different bus encoding scheme in terms of area, timing overhead and efficiency of power reduction and switching activity reduction.