A processing element architecture for high-density focal plane analog programmable array processors

Author

Liñán-Cembrano, G. ; Espejo, S. ; Dominguez-Castro, R. ; Rodriguez-Vázquez, A.

Author_Institution

Inst. de Microelectron., CSIC, Seville, Spain

Volume

3

fYear

2002

fDate

2002

Abstract

The architecture of the elementary Processing Element - PE - used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3×3 convolution masks. The vision chip has been implemented in a standard 0.35 μm CMOS technology. The main PE related figures are: 180 cells/mm², 18 MOPS/cell, and 180 μW/cell.

Keywords

CMOS analogue integrated circuits; CMOS image sensors; analogue processing circuits; image processing equipment; parallel architectures; programmable circuits; 0.35 micron; CMOS technology; analog programmable array processor; bifurcated data flow vision algorithms; convolution masks; focal plane array processor; high-density array processors; processing element architecture; vision chip; CMOS image sensors; CMOS technology; Circuits; Convolution; Electronic mail; Energy consumption; Image processing; Machine vision; Process design; Retina;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010230

Filename

1010230