Simulation of logic/IDDQ tests for resistive shorts in logic circuits by using simplicial approximation

Logic circuits in the presence of resistive shorts often exhibit analog behavior which can be computationally expensive to simulate. This paper introduces a numerical method called simplicial approximation for its application to simulation of logic/IDDQ tests for resistive shorts. Example circuits with transistor gate-to-drain and gate-to-source shorts are used to demonstrate the feasibility of the method. The results, when compared to SPICE simulation, show a 95% reduction in computational time at the price of less numerical accuracy, which is generally acceptable in this application.